FIG. 1 shows a circuit diagram for a conventional digital low drop-out (LDO) voltage regulator circuit 10. The circuit 10 includes an array 12 of transistor switches 14(1)-14(n), wherein each transistor switch 14 has a first conduction terminal (for example, a source terminal) connected to a supply voltage node Vdd and a second conduction terminal (for example, a drain terminal) connected to an output node Vout. A digital controller 16 generates a plurality of digital control signals 18(1)-18(n) that are applied to the control terminals (for example, a gate terminal) of the transistor switches 14(1)-14(n), respectively. The transistor switches 14(1)-14(n) comprise p-channel MOSFET devices. In response to assertion (for example, logic low) of a digital control signal 18, the corresponding transistor switch 14 is turned on to source current to the load 22 and to the output capacitor 24 to develop the regulated output voltage at the output node Vout. A comparator 28 has a first input that receives the regulated output voltage at the output node Vout and a second input that receives a reference voltage Vref. The comparator 28 compares Vout to Vref and generates a digital comparison signal 30 that is applied to an input of the digital controller 16. Depending on the logic state of the digital comparison signal 30, the digital controller 16 adjusts the number of digital control signals 18(1)-18(n) that are asserted. For example, if Vout exceeds Vref then there is a decrease in the number of digital control signals 18(1)-18(n) that are asserted and this accordingly decreases the number of transistor switches 14(1)-14(n) that are turned on. Conversely, if Vref exceeds Vout then there is an increase in the number of digital control signals 18(1)-18(n) that are asserted and this accordingly increases the number of transistor switches 14(1)-14(n) that are turned on.
In an example implementation, the digital controller 16 may be implemented as a multi-bit bidirectional shift register having a serial input configured to receive the digital comparison signal 30 and a parallel output configured to generate the digital control signals 18(1)-18(n). In response to a logic state of the comparison signal 30 indicating that Vout exceeds Vref, the multi-bit shift register will shift in a first direction which reduces the number of bits of the shift register that are at the logic low state. If the logic state of the comparison signal 30 instead indicates that Vref exceeds Vout, the multi-bit shift register will shift in a second direction which increases the number of bits of the shift register that are at the logic low state.
There are a number of advantages of digital LDO voltage regulators like that shown in FIG. 1; those advantages include: low supply voltage operation and scalability. However, there are drawbacks including: a trade-off between power and speed, a need for a large output capacitor 24, a large ripple on the regulator output voltage Vout and a reduced accuracy of the regulated output voltage. There is a need in the art to address at least some of the foregoing drawbacks while maintaining the advantages of the digital LDO solution.